~ruther/verilog-riscv-semestral-project (740085c87e5cdab5e4d96e696df87f4a30e6f09f): .gitmodules

~ruther/verilog-riscv-semestral-project

ref: 740085c87e5cdab5e4d96e696df87f4a30e6f09f verilog-riscv-semestral-project/.gitmodules -rwxr-xr-x 137 bytes

740085c8 — Rutherther fix: lui, force rs1 zero, always add 1 year, 5 months ago

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[submodule "tests/official/riscv-tests"]
	path = tests/official/riscv-tests
	url = https://github.com/riscv-software-src/riscv-tests.git