~ruther/verilog-riscv-semestral-project (740085c87e5cdab5e4d96e696df87f4a30e6f09f): .gitignore

~ruther/verilog-riscv-semestral-project

ref: 740085c87e5cdab5e4d96e696df87f4a30e6f09f verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 110 bytes

740085c8 — Rutherther fix: lui, force rs1 zero, always add 1 year, 7 months ago

.DS_Store
.idea
*.log
tmp/

.direnv/
obj_dir/
*.vcd

out/

waves/
programs/bin/
*.o
*.bin
*.dat

__pycache__/