~ruther/verilog-riscv-semestral-project

ref: 73cf8a16605792f3455e04745c5e0007e1f08be5 verilog-riscv-semestral-project/testbench d---------
73cf8a16 — Rutherther tests: fix simple cpu test to use memory.dump and doesnt wait for ebreak 1 year, 4 months ago
..
-rwxr-xr-x
tb_alu.sv
1.0 KiB
-rwxr-xr-x
tb_control_unit.sv
3.2 KiB
-rwxr-xr-x
tb_cpu_program.sv
1.9 KiB
-rwxr-xr-x
tb_cpu_simple.sv
2.5 KiB
-rwxr-xr-x
tb_ram.sv
632 bytes
-rwxr-xr-x
tb_register_file.sv
837 bytes
Do not follow this link