~ruther/verilog-riscv-semestral-project (73cf8a16605792f3455e04745c5e0007e1f08be5): .gitmodules

~ruther/verilog-riscv-semestral-project

ref: 73cf8a16605792f3455e04745c5e0007e1f08be5 verilog-riscv-semestral-project/.gitmodules -rwxr-xr-x 137 bytes

73cf8a16 — Rutherther tests: fix simple cpu test to use memory.dump and doesnt wait for ebreak 1 year, 6 months ago

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[submodule "tests/official/riscv-tests"]
	path = tests/official/riscv-tests
	url = https://github.com/riscv-software-src/riscv-tests.git