~ruther/verilog-riscv-semestral-project

ref: 732301c9f816051cb1b7937d011d3b21d10f68c2 verilog-riscv-semestral-project/programs/link.ld -rwxr-xr-x 291 bytes
732301c9 — Rutherther chore: move inital sp to 1020 1 year, 5 months ago 
                                                                                
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21

MEMORY
{
    ram : ORIGIN = 0x00000000, LENGTH = 1K - 1
}

SECTIONS
{
	.text = 0x0;
    .bss : {
        __bss_start = .;
        *(.bss)
        *(COMMON)
        __bss_end = .;
    } > ram
    .stack : {
        __stack_start = .;
        *(.stack)
        __stack_end = .;
    } > ram
}
Do not follow this link