~ruther/verilog-riscv-semestral-project

ref: 732301c9f816051cb1b7937d011d3b21d10f68c2 verilog-riscv-semestral-project/programs/branches.c -rwxr-xr-x 649 bytes
732301c9 — Rutherther chore: move inital sp to 1020 2 years ago 
                                                                                
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42

void main()
{
    int *result_address = 0;
    int a = 1;
    int b = 5;

    if (a < b) {
        *result_address = 1;
    } else {
        *result_address = 2;
    }

    if (a >= b) {
        *result_address = 1;
    } else {
        *result_address = 2;
    }

    if (a != b) {
        *result_address = 1;
    } else {
        *result_address = 2;
    }

    if (a == b) {
        *result_address = 1;
    } else {
        *result_address = 2;
    }

    if (a <= b) {
        *result_address = 1;
    } else {
        *result_address = 2;
    }

    if (a > b) {
        *result_address = 1;
    } else {
        *result_address = 2;
    }
}