~ruther/verilog-riscv-semestral-project

ref: 6ce1c83859b56b514f0a4536ddb388cacc77773e verilog-riscv-semestral-project/programs/start.S -rwxr-xr-x 84 bytes
6ce1c838 — Rutherther chore: remove gcc generated file 1 year, 7 months ago 
                                                                                
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.global _start

.text
_start:
    addi sp, x0, 127
    call main
_loop:
    j _loop
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