~ruther/verilog-riscv-semestral-project

ref: 6ce1c83859b56b514f0a4536ddb388cacc77773e verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 52 bytes
6ce1c838 — Rutherther chore: remove gcc generated file 2 years ago 
                                                                                
1
2
3
4
5
6
7
8

.DS_Store
.idea
*.log
tmp/

.direnv/
obj_dir/
*.vcd