~ruther/verilog-riscv-semestral-project

ref: 69ced879bbbaf6d106ac95a8ee8e6a6872177c83 verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 37 bytes
69ced879 — Rutherther fix: make rd1, rd2 in register_file regs 2 years ago 
                                                                                
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.direnv/