~ruther/verilog-riscv-semestral-project

ref: 5fe030988a21d47dd13af35a9b8697b2181cb6b7 verilog-riscv-semestral-project/programs/branches.c -rwxr-xr-x 468 bytes
5fe03098 — Rutherther chore: trace memory array 1 year, 5 months ago 
                                                                                
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void main()
{
    int a = 1;
    int b = 5;
    int c = 0;

    if (a < b) {
        c = 1;
    } else {
        c = 2;
    }

    if (a >= b) {
        c = 1;
    } else {
        c = 2;
    }

    if (a != b) {
        c = 1;
    } else {
        c = 2;
    }

    if (a == b) {
        c = 1;
    } else {
        c = 2;
    }

    if (a <= b) {
        c = 1;
    } else {
        c = 2;
    }

    if (a > b) {
        c = 1;
    } else {
        c = 2;
    }

}
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