~ruther/verilog-riscv-semestral-project

ref: 586cf7122913dbe1faece5e92b9da4bfc0d36403 verilog-riscv-semestral-project/src/stages/fetch.sv -rw-r--r-- 339 bytes
586cf712 — Rutherther chore: clearer naming 1 year, 3 months ago 
                                                                                
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import cpu_types::*;

module fetch(
  input        clk,
  input        flush,
  input [31:0] pc,
  input [31:0] mem_instruction,

  output       stage_status_t stage_out
);
  assign stage_out.instruction.instruction = mem_instruction;
  assign stage_out.pc = pc;

  assign stage_out.valid = !flush;
  assign stage_out.ready = 1;
endmodule
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