~ruther/verilog-riscv-semestral-project (51842d387ac593fdcad90d2ed22e258a1c6780ee): programs/branches.c

void main()
{
    int *result_address = 0;
    int a = 1;
    int b = 5;

    if (a < b) {
        *result_address = 1;
    } else {
        *result_address = 2;
    }

    if (a >= b) {
        *result_address = 1;
    } else {
        *result_address = 2;
    }

    if (a != b) {
        *result_address = 1;
    } else {
        *result_address = 2;
    }

    if (a == b) {
        *result_address = 1;
    } else {
        *result_address = 2;
    }

    if (a <= b) {
        *result_address = 1;
    } else {
        *result_address = 2;
    }

    if (a > b) {
        *result_address = 1;
    } else {
        *result_address = 2;
    }
}