~ruther/verilog-riscv-semestral-project (38e84297e0e6abf0ec14d91878d5210792b801bd): .gitmodules

~ruther/verilog-riscv-semestral-project

ref: 38e84297e0e6abf0ec14d91878d5210792b801bd verilog-riscv-semestral-project/.gitmodules -rwxr-xr-x 137 bytes

38e84297 — Rutherther fix: shift left only by 5 bits 1 year, 5 months ago

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[submodule "tests/official/riscv-tests"]
	path = tests/official/riscv-tests
	url = https://github.com/riscv-software-src/riscv-tests.git