~ruther/verilog-riscv-semestral-project

ref: 300c2dd744c0a39f8ca60ce97c3015c7af4c27cf verilog-riscv-semestral-project/src/ram.sv -rwxr-xr-x 221 bytes
300c2dd7 — Rutherther feat: add program counter 1 year, 7 months ago 
                                                                                
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module ram (
  input         clk, we,
  input [31:0]  a, wd,
  output [31:0] rd);

  reg [31:0]    RAM[0:127];

  assign rd = RAM[a[8:2]]; // word aligned

  always @(posedge clk)
    if(we) RAM[a[8:2]] <= wd;

endmodule
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