~ruther/verilog-riscv-semestral-project

ref: 300c2dd744c0a39f8ca60ce97c3015c7af4c27cf verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 52 bytes
300c2dd7 — Rutherther feat: add program counter 2 years ago 
                                                                                
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.DS_Store
.idea
*.log
tmp/

.direnv/
obj_dir/
*.vcd