~ruther/verilog-riscv-semestral-project

ref: 2929a779a9d6e451c15f91ac7124f4081e2a04b4 verilog-riscv-semestral-project/src/cpu_types.sv -rwxr-xr-x 291 bytes
2929a779 — Rutherther test: add basic testbenches 1 year, 7 months ago 
                                                                                
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package cpu_types;
  typedef enum bit[0:0] { PC_PLUS, PC_ALU } pc_source_t;
  typedef enum bit[0:0] { REG_FILE_RS1, PC } alu_1_source_t;
  typedef enum bit[0:0] { REG_FILE_RS2, IMMEDIATE } alu_2_source_t;
  typedef enum bit[1:0] { RD_ALU, RD_PC_PLUS, RD_MEMORY } reg_rd_source_t;
endpackage
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