~ruther/verilog-riscv-semestral-project

ref: 280332ea3bcdd58544d3b1606eedd54fda0f1611 verilog-riscv-semestral-project/tests d---------
280332ea — Rutherther fix: make Makefile work with memory load, write files 2 years ago
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comp_list.lst
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custom/
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official/
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run.py
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test_types.py
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