~ruther/verilog-riscv-semestral-project

ref: 27fcb8d9421b49a1d1545cb4fb80f9c6f03ebaf8 verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 52 bytes
27fcb8d9 — Rutherther fix: do not use immediate in alu src for SB 2 years ago 
                                                                                
1
2
3
4
5
6
7
8

.DS_Store
.idea
*.log
tmp/

.direnv/
obj_dir/
*.vcd