~ruther/verilog-riscv-semestral-project

ref: 1d7c9233527974f1bfd8db7e0027d5871911b997 verilog-riscv-semestral-project/tests/official/env/p/link.ld -rwxr-xr-x 33 bytes
1d7c9233 — Rutherther chore: add python cache to gitignore 1 year, 5 months ago 
                                                                                
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{
  .text.init = 0x0;
}
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