~ruther/verilog-riscv-semestral-project

ref: 1d7c9233527974f1bfd8db7e0027d5871911b997 verilog-riscv-semestral-project/tests/comp_list.lst -rwxr-xr-x 197 bytes
1d7c9233 — Rutherther chore: add python cache to gitignore 1 year, 5 months ago 
                                                                                
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src/cpu_types.sv
src/instruction_decoder.sv
src/control_unit.sv
src/alu.sv
src/register_file.sv
src/program_counter.sv
src/ram.sv
src/cpu.sv
src/file_program_memory.sv

testbench/tb_cpu_program.sv
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