~ruther/verilog-riscv-semestral-project (18eeb2c56b849ad7bffa04c2e212619237449216): programs/tests.c

~ruther/verilog-riscv-semestral-project

ref: 18eeb2c56b849ad7bffa04c2e212619237449216 verilog-riscv-semestral-project/programs/tests.c -rwxr-xr-x 132 bytes

18eeb2c5 — Rutherther tests: compile only once, copy proram, memory files to correct locations 1 year, 5 months ago

void main()
{
	signed char a = -10;
	signed char b = a << 1;
	unsigned char c = ((unsigned char)b) >> 1;
	signed char d = b >> 1;
}