~ruther/verilog-riscv-semestral-project

ref: 18eeb2c56b849ad7bffa04c2e212619237449216 verilog-riscv-semestral-project/programs/start.S -rwxr-xr-x 94 bytes
18eeb2c5 — Rutherther tests: compile only once, copy proram, memory files to correct locations 1 year, 5 months ago 
                                                                                
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.global _start

.text
_start:
    addi sp, x0, 1020
    call main
loop:
    ebreak
    j loop
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