~ruther/verilog-riscv-semestral-project

ref: 18eeb2c56b849ad7bffa04c2e212619237449216 verilog-riscv-semestral-project/programs/add.c -rwxr-xr-x 171 bytes
18eeb2c5 — Rutherther tests: compile only once, copy proram, memory files to correct locations 1 year, 5 months ago 
                                                                                
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int add(int a, int b)
{
    return a + b;
}

void main()
{
    int a = 20;
    int b = 30;
    int c = add(a, b);

    int* result_address = 0;
    *result_address = c;
}
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