~ruther/verilog-riscv-semestral-project (18eeb2c56b849ad7bffa04c2e212619237449216): .gitmodules

~ruther/verilog-riscv-semestral-project

ref: 18eeb2c56b849ad7bffa04c2e212619237449216 verilog-riscv-semestral-project/.gitmodules -rwxr-xr-x 137 bytes

18eeb2c5 — Rutherther tests: compile only once, copy proram, memory files to correct locations 1 year, 6 months ago

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[submodule "tests/official/riscv-tests"]
	path = tests/official/riscv-tests
	url = https://github.com/riscv-software-src/riscv-tests.git