~ruther/verilog-riscv-semestral-project (0e23dce51761469332c4b654818475721e29d171): src/cpu_types.sv

~ruther/verilog-riscv-semestral-project

ref: 0e23dce51761469332c4b654818475721e29d171 verilog-riscv-semestral-project/src/cpu_types.sv -rwxr-xr-x 291 bytes

0e23dce5 — Rutherther fix(register_file): output register if addr not zero 1 year, 7 months ago

package cpu_types;
  typedef enum bit[0:0] { PC_PLUS, PC_ALU } pc_source_t;
  typedef enum bit[0:0] { REG_FILE_RS1, PC } alu_1_source_t;
  typedef enum bit[0:0] { REG_FILE_RS2, IMMEDIATE } alu_2_source_t;
  typedef enum bit[1:0] { RD_ALU, RD_PC_PLUS, RD_MEMORY } reg_rd_source_t;
endpackage

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