~ruther/verilog-riscv-semestral-project

ref: 0e23dce51761469332c4b654818475721e29d171 verilog-riscv-semestral-project/.envrc -rwxr-xr-x 10 bytes
0e23dce5 — Rutherther fix(register_file): output register if addr not zero 2 years ago 
                                                                                
1

use flake