~ruther/verilog-riscv-semestral-project (0a9a14b7e6d78454c80c2331b0bd0150bc18d631): programs/tests.c

~ruther/verilog-riscv-semestral-project

ref: 0a9a14b7e6d78454c80c2331b0bd0150bc18d631 verilog-riscv-semestral-project/programs/tests.c -rwxr-xr-x 132 bytes

0a9a14b7 — Rutherther test: add ram test 1 year, 7 months ago

void main()
{
	signed char a = -10;
	signed char b = a << 1;
	unsigned char c = ((unsigned char)b) >> 1;
	signed char d = b >> 1;
}