~ruther/verilog-riscv-semestral-project

ref: 0a9a14b7e6d78454c80c2331b0bd0150bc18d631 verilog-riscv-semestral-project/programs/start.S -rwxr-xr-x 84 bytes
0a9a14b7 — Rutherther test: add ram test 1 year, 7 months ago 
                                                                                
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.global _start

.text
_start:
    addi sp, x0, 127
    call main
_loop:
    j _loop
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