~ruther/verilog-riscv-semestral-project

ref: 02405eecab38bfa1d85e88d908b52a589ee53d30 verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 52 bytes
02405eec — Rutherther fix: force alu operation to addition for storing memory and pc 2 years ago 
                                                                                
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.DS_Store
.idea
*.log
tmp/

.direnv/
obj_dir/
*.vcd