~ruther/verilog-riscv-semestral-project

verilog-riscv-semestral-project/testbench/tb_ram.sv -rw-r--r-- 818 bytes
79c7be5c — Rutherther 2 years ago main 
chore: remove unnecessary executable flags

Closes #4.
db85fb35 — Rutherther 2 years ago 
tests: fix ram and control_unit tests to match newest architecture
0a9a14b7 — Rutherther 2 years ago 
test: add ram test