~ruther/verilog-riscv-semestral-project: testbench/tb_ram.sv 79c7be5c1c8ae2aea07f48d32abca650d24e8045

~ruther/verilog-riscv-semestral-project

ref: 79c7be5c1c8ae2aea07f48d32abca650d24e8045 verilog-riscv-semestral-project/testbench/tb_ram.sv -rw-r--r-- 818 bytes

79c7be5c — Rutherther 1 year, 3 months ago main

chore: remove unnecessary executable flags

Closes #4.

db85fb35 — Rutherther 1 year, 4 months ago

tests: fix ram and control_unit tests to match newest architecture

0a9a14b7 — Rutherther 1 year, 5 months ago

test: add ram test