~ruther/verilog-riscv-semestral-project: testbench/tb_alu.sv fb02ebb264bda787ca3441964dfa1fe6e69ca6ef

~ruther/verilog-riscv-semestral-project

ref: fb02ebb264bda787ca3441964dfa1fe6e69ca6ef verilog-riscv-semestral-project/testbench/tb_alu.sv -rwxr-xr-x 1.0 KiB

707b5bfc — Rutherther 1 year, 7 months ago

chore: add makefile for both verilog and c

2929a779 — Rutherther 1 year, 7 months ago

test: add basic testbenches