~ruther/verilog-riscv-semestral-project: tests/test_types.py f8e4e3ed2dc54033786b23aa41cd88ba92eb83e2

~ruther/verilog-riscv-semestral-project

ref: f8e4e3ed2dc54033786b23aa41cd88ba92eb83e2 verilog-riscv-semestral-project/tests/test_types.py -rwxr-xr-x 928 bytes

308a1462 — Rutherther 1 year, 6 months ago

tests: add register dump, printing

51842d38 — Rutherther 1 year, 6 months ago

feat: add support for official tests