~ruther/verilog-riscv-semestral-project: tests/official/Makefile f8e4e3ed2dc54033786b23aa41cd88ba92eb83e2

~ruther/verilog-riscv-semestral-project

ref: f8e4e3ed2dc54033786b23aa41cd88ba92eb83e2 verilog-riscv-semestral-project/tests/official/Makefile -rwxr-xr-x 618 bytes

18eeb2c5 — Rutherther 1 year, 8 months ago

tests: compile only once, copy proram, memory files to correct locations

51842d38 — Rutherther 1 year, 8 months ago

feat: add support for official tests