~ruther/verilog-riscv-semestral-project: testbench/tb_alu.sv f8e4e3ed2dc54033786b23aa41cd88ba92eb83e2

~ruther/verilog-riscv-semestral-project

ref: f8e4e3ed2dc54033786b23aa41cd88ba92eb83e2 verilog-riscv-semestral-project/testbench/tb_alu.sv -rwxr-xr-x 1.0 KiB

707b5bfc — Rutherther 1 year, 7 months ago

chore: add makefile for both verilog and c

2929a779 — Rutherther 1 year, 7 months ago

test: add basic testbenches