~ruther/verilog-riscv-semestral-project: .gitignore f8bf441ea1e4cf7b0e609b80aecca786fa2a48f3

~ruther/verilog-riscv-semestral-project

ref: f8bf441ea1e4cf7b0e609b80aecca786fa2a48f3 verilog-riscv-semestral-project/.gitignore -rwxr-xr-x 37 bytes

9c81ece2 — Rutherther 2 years ago

chore: add gitignore