~ruther/verilog-riscv-semestral-project: testbench/tb_control_unit.sv e7b5d989532b0690f2b0ef3a1b7a0072903c0d51

~ruther/verilog-riscv-semestral-project

ref: e7b5d989532b0690f2b0ef3a1b7a0072903c0d51 verilog-riscv-semestral-project/testbench/tb_control_unit.sv -rwxr-xr-x 3.2 KiB

707b5bfc — Rutherther 2 years ago

chore: add makefile for both verilog and c

acf0f724 — Rutherther 2 years ago

feat: implement sb, sh, lb, lh support via masking

2929a779 — Rutherther 2 years ago

test: add basic testbenches