~ruther/verilog-riscv-semestral-project: testbench/tb_alu.sv e7b5d989532b0690f2b0ef3a1b7a0072903c0d51

~ruther/verilog-riscv-semestral-project

ref: e7b5d989532b0690f2b0ef3a1b7a0072903c0d51 verilog-riscv-semestral-project/testbench/tb_alu.sv -rwxr-xr-x 1.0 KiB

707b5bfc — Rutherther 1 year, 8 months ago

chore: add makefile for both verilog and c

2929a779 — Rutherther 1 year, 8 months ago

test: add basic testbenches