~ruther/verilog-riscv-semestral-project

ref: e7b5d989532b0690f2b0ef3a1b7a0072903c0d51 verilog-riscv-semestral-project/testbench d--------- 
test: add cpu testbenches for c programs

test: add ram test

chore: add makefile for both verilog and c

feat: implement sb, sh, lb, lh support via masking

test: add simple cpu test

test: add basic testbenches
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