~ruther/verilog-riscv-semestral-project: src/ram.sv e7b5d989532b0690f2b0ef3a1b7a0072903c0d51

~ruther/verilog-riscv-semestral-project

ref: e7b5d989532b0690f2b0ef3a1b7a0072903c0d51 verilog-riscv-semestral-project/src/ram.sv -rwxr-xr-x 498 bytes

ca9604e2 — Rutherther 1 year, 5 months ago

fix: offset ram by bytes, not bits

acf0f724 — Rutherther 1 year, 5 months ago

feat: implement sb, sh, lb, lh support via masking

8adc02d7 — Rutherther 1 year, 5 months ago

feat: add basic ram, alu, and register file