~ruther/verilog-riscv-semestral-project: src/ram.sv e44bfc9ea42a45f5776158e8e51c025f185b4f56

~ruther/verilog-riscv-semestral-project

ref: e44bfc9ea42a45f5776158e8e51c025f185b4f56 verilog-riscv-semestral-project/src/ram.sv -rwxr-xr-x 221 bytes

8adc02d7 — Rutherther 2 years ago

feat: add basic ram, alu, and register file