~ruther/verilog-riscv-semestral-project

ref: df876b38b787b7f1e9120775311a0b1a17e2758b verilog-riscv-semestral-project/programs/add.c -rwxr-xr-x 171 bytes
feat: store c results in memory addr 0
feat: add basic testing programs
Do not follow this link