~ruther/verilog-riscv-semestral-project

ref: db85fb354b873f3ab5e5e936b4412a7d828f0ca7 verilog-riscv-semestral-project/tests/official/env/p/riscv_test.h -rwxr-xr-x 8.2 KiB 
tests: add register dump, printing

feat: add support for official tests
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