~ruther/verilog-riscv-semestral-project: src/cpu_types.sv d4e70aa69c3671bba9e02d198267f09cfc493a11

~ruther/verilog-riscv-semestral-project

ref: d4e70aa69c3671bba9e02d198267f09cfc493a11 verilog-riscv-semestral-project/src/cpu_types.sv -rwxr-xr-x 368 bytes

acf0f724 — Rutherther 1 year, 5 months ago

feat: implement sb, sh, lb, lh support via masking

b7fa590c — Rutherther 1 year, 5 months ago

chore: add cpu types for various sources

Better orientation by name instead of
number