~ruther/verilog-riscv-semestral-project: testbench/tb_control_unit.sv c682cc068ee41da1b00fbd51dfb79f9cd5560d0d

~ruther/verilog-riscv-semestral-project

ref: c682cc068ee41da1b00fbd51dfb79f9cd5560d0d verilog-riscv-semestral-project/testbench/tb_control_unit.sv -rwxr-xr-x 3.2 KiB

707b5bfc — Rutherther 2 years ago

chore: add makefile for both verilog and c

acf0f724 — Rutherther 2 years ago

feat: implement sb, sh, lb, lh support via masking

2929a779 — Rutherther 2 years ago

test: add basic testbenches