~ruther/verilog-riscv-semestral-project: testbench/tb_alu.sv c682cc068ee41da1b00fbd51dfb79f9cd5560d0d

~ruther/verilog-riscv-semestral-project

ref: c682cc068ee41da1b00fbd51dfb79f9cd5560d0d verilog-riscv-semestral-project/testbench/tb_alu.sv -rwxr-xr-x 1.0 KiB

707b5bfc — Rutherther 1 year, 7 months ago

chore: add makefile for both verilog and c

2929a779 — Rutherther 1 year, 7 months ago

test: add basic testbenches