~ruther/verilog-riscv-semestral-project

ref: c5e322db080e580a25dafe64d29405db34adec57 verilog-riscv-semestral-project/tests/official/official_tests.py -rwxr-xr-x 1.4 KiB
308a1462 — Rutherther 2 years ago 
tests: add register dump, printing
51842d38 — Rutherther 2 years ago 
feat: add support for official tests