~ruther/verilog-riscv-semestral-project: testbench/tb_register_file.sv bde9255cf35820314e882969060f77f5cbd6c460

~ruther/verilog-riscv-semestral-project

ref: bde9255cf35820314e882969060f77f5cbd6c460 verilog-riscv-semestral-project/testbench/tb_register_file.sv -rwxr-xr-x 837 bytes

707b5bfc — Rutherther 2 years ago

chore: add makefile for both verilog and c

2929a779 — Rutherther 2 years ago

test: add basic testbenches