~ruther/verilog-riscv-semestral-project

ref: bc02aba5f50d84e93657a0601f713d990ecb8f11 verilog-riscv-semestral-project/testbench/tb_cpu_simple.sv -rwxr-xr-x 2.3 KiB 
test: add simple cpu test
Do not follow this link