~ruther/verilog-riscv-semestral-project

ref: b89bec430c94042ce0fce7527aad91a42af9f00b verilog-riscv-semestral-project/testbench/tb_alu.sv -rwxr-xr-x 1.0 KiB
707b5bfc — Rutherther 2 years ago 
chore: add makefile for both verilog and c
2929a779 — Rutherther 2 years ago 
test: add basic testbenches